1. Field of the Invention
This invention relates to the design of power converters and, more particularly, to designing current-sense circuitry in power converters.
2. Description of the Related Art
Power consumption of integrated circuits (ICs) has been on the rise with the development of high performance, high density systems, most notably central processing units (CPUs) manufactured by companies like Intel and AMD. For example, the highest density processors from manufacturers such as Intel went from a power consumption rate of about 30 Watts at 3.3 V to a power consumption rate of about 90 Watts at 1.5 V. A simple application of the power-voltage-current relationship reveals that the total current consumed by these chips has increased from nine amps to about 60 amps in a very short time period. Similar analogies may be applied to all larger digital integrated circuits. This rapid evolution has presented new and significant problems in delivery of the power to and removal of waste heat from the ICs. High-current/low-voltage ICs require a very clean and stable source of DC power. The power source must be capable of delivering very fast current transients. The electronic path to these loads must also have low resistance and inductance (a 1.5V supply would be completely dropped across a 25 mΩ resistance at 60 Amps).
In most current IC systems, an AC supply voltage is typically converted to an intermediate DC voltage and routed to the point-of-load (POL), where it is locally converted down to the required voltage. This technique commonly referred to as “Distributed Power Architecture” (DPA) is illustrated in FIG. 1. As shown in DPA system 120 of FIG. 1, an AC to DC voltage converter 122 may produce an intermediate DC voltage Vx, which may be routed to individual local DC to DC (DC-DC) converters 124, 126, 128, and 130, which in turn may provide the required DC voltages V1, V2, V3, and V4, respectively, to their corresponding POLs. With a DPA, errors may be reduced since the distance traveled by a high-current signal is minimized, thus reducing I×R (resistive) and L di/dt (inductive) errors.
The DC-to-DC conversion in DC-DC converters, such as those shown in FIG. 1, is often performed by having switching power regulators/converters, also known as step-down regulators/converters, converting a higher voltage (e.g. 12V) to a lower value as required by the powered load devices. These switching power converters typically require current-sensing to implement both control and protection functions. Current-sharing in multi-phase power converters and current-mode control are examples of control functions. Overload protection (including short-circuit protection) also require current-sensing.
Most existing current-sensing methods are typically divided into “lossy” and “lossless” categories. The lossless methods oftentimes make use of existing parasitic resistances, for instance the RDS—on on-state resistance of a power MOSFET, the series resistance of an inductor, or the trace resistance of a printed circuit board (PCB). These methods generally do not introduce additional power losses. They are most attractive in high-current applications where an additional sense-resistor can reduce the overall efficiency of the power converter. However they suffer from low accuracy due to tolerances and temperature dependency of the parasitic resistance. The addition of an accurate sense-resistor—e.g. in series with a power MOSFET or in series with the load—as part of a lossy current-sensing method may improve accuracy at the expense of increased power losses.
FIG. 2 shows one example of a switching voltage (power) regulator, a synchronous buck converter in this case, which generates a DC output voltage Vout from a DC input voltage Vin. Two power NMOS devices, a high-side NMOS device 104 and a low-side NMOS device 106, may be controlled by driver 102 to alternatively direct the load current IL to input VIN and ground. Inductor 108 and capacitor 110 may be used to smooth out the voltage waveform generated at node SW, resulting in output voltage Vout generated across load 112. FIG. 3a shows key waveforms such as waveform 202 for gate drive GL (voltage across node GL and ground), waveform 204 for gate drive GH-SW (voltage across nodes GH and SW), waveform 206 for the switch node SW (voltage across SW and ground) and waveform 208 for the load current IL. As seen in FIG. 3a, the ripple in load current 208 is small enough for IL to remain positive during the entire switching period. For small inductor values of inductor 108, the larger ripple in load current IL may result in negative IL for at least a portion of the switching period as shown by waveform 308 in FIG. 3b. The load current can be negative throughout the entire switching period, if power is transferred from load 112 to input Vin. Therefore, any practical current sensing method for power switches 104 and 106 would require handling bidirectional currents through the switches (NMOS devices 104 and 106).
Certain FET based current-sense methods can result in virtually lossless measurement of high current levels. In applications where a power MOSFET is integrated with its driver, a matching current-sense MOSFET connected in parallel to the power device can be used to generate a current that is a small fraction of the power device current. Typically, an integrated power MOSFET has multiple poly gate fingers. The sense FET can consist of one or more matching poly gate fingers. The ratio of the channel width of the power device to the channel width of the sense device can be chosen to be high (around 1000) to keep the power losses low. Ideally, it is desirable to have the ratio of the sense FET current to the power switch current be process variation and temperature independent to obtain an accurate current measurement. It should be noted that while only the use of NMOS power switches is mentioned, current-sense methods can be implemented with both NMOS and/or PMOS power switches.
FIG. 4 shows a FET based current-sense method, with sense FET 404 configured to sense current for switching transistor 402. The sensed current Isense is conducted by Rsense resistor 406, which can be configured either on-chip or off-chip. Analyzing the circuit in FIG. 4, the following relationships can be established:
                                                        I              switch                                      I              sense                                =                                                    R                                  on_                  ⁢                  404                                            +                              R                sense                                                    R                              on_                ⁢                402                                                    ,                            (        1        )            
where Ron—404 is the effective resistance of NMOS device 404 and Ron—402 is the effective channel resistance of NMOS device 402 in its on state. In this case, both NMOS devices 402 and 404 are the same type MOSFET devices with the same channel length L. Furthermore, if NMOS device 404 has been designed such that VGS-VTH>>VDS, then
                                                        R                              on_                ⁢                404                                                    R                              on_                ⁢                402                                              ≅                                    W              402                                      W              404                                      ,                            (        2        )            where W402 represents the channel width of NMOS device 402 and W404 represents the channel width of NMOS device 404. It follows from equations 1 and 2 that:
                                                        I              switch                                      I              sense                                =                                                    W                402                                            W                404                                      *                          [                              1                +                                  (                                                                                    R                        sense                                                                    R                                                  on_                          ⁢                          402                                                                                      *                                                                  W                        404                                                                    W                        402                                                                              )                                            ]                                      ,        and                            (        3        )                                                      I            switch                                V            sense                          =                                            I              switch                                                      I                sense                            *                              R                sense                                              =                                                    W                402                                            W                404                                      *                                          [                                                      1                                          R                      sense                                                        +                                      (                                                                  1                                                  R                                                      on_                            ⁢                            402                                                                                              *                                                                        W                          404                                                                          W                          402                                                                                      )                                                  ]                            .                                                          (        4        )            On important drawback of the FET based current-sense method shown in FIG. 4 is that
            I      switch              I      sense        ⁢          ⁢  and  ⁢          ⁢            I      switch              V      sense      are both affected by process variations and temperature.
FIG. 5 shows another current-sensing method that can be used for measuring the current of an integrated switching device 502[1]. An amplifier 508 imposes the VDS voltage of switching device 502 across sense FET 504. Furthermore the same VGS voltage is applied to switching device 502 and sense FET 504. As a result
                                                        I              switch                                      I              sense                                =                                    W              502                                      W              504                                      ,                            (        5        )            where W502 represents the channel width of switching device 502 and W504 represents the channel width of sense FET device 504. The ratio
      I    switch        I    sense  in equation 5 is fabrication process and temperature independent. This method, however, can generally not be used in applications where the measured power switch current Iswitch is bi-directional. Furthermore, in applications where the drain voltage of switching device 502 switches between a low on-state and a high off-state voltage, the input In+ of amplifier 508 can be exposed to both high voltage values and high dv/dt transitions. Therefore, a high-speed, high-voltage amplifier is typically required. Designing a high-speed amplifier with high-voltage devices can be difficult.
FIG. 6 shows a current-sense method that utilizes circuit blocks comprising sense FETs 604 and 610, and amplifiers 608 and 614, respectively, to generate a scaled-down copy of the switch current Iswitch for both positive and negative Iswitch values, for sensing current for switching device 602[2]. Specifically Isense—p is proportional to the power switch current Iswitch for positive values of Iswitch and zero for negative values of Iswitch. Isense—n is proportional to the power switch current Iswitch for negative values of Iswitch and zero for positive values of Iswitch. The sum sense current of the two component sense currents (Isense—n+Isense—p) will have a proportionality factor to switch current Iswitch that is process variation and temperature independent. Since both amplifiers 608 and 614 are connected to the drain of switching device 602, they can be exposed to both high voltage values and high dv/dt transitions, requiring a high-speed, high-voltage amplifier implementation. Zero-current crossover distortion due to different input offsets of amplifiers 608 and 614 may present a potential issue. Specifically, if the value of switch current Iswitch is around zero, the output currents of both amplifiers 608 and 614 can be zero.
FIG. 7 shows yet another current-sensing method, where matching devices 706 and 708 scale the switch voltage Vswitch down to Vsense when switching device 704 is conducting[3]. The ratio of Vsense to Vswitch is in this case:
                                                        V              switch                                      V              sense                                =                                                    W                706                                                              W                  706                                +                                  W                  708                                                      =                          k              <              1                                      ,                            (        6        )            where W706 represents the channel width of switching device 706 and W708 represents the channel width of switching device 708. Vsense forms the input to amplifier 714. If sensing device 710 matches switching device 704, then
                                                        I              switch                                      I              sense                                =                                                    W                704                                            W                710                                      *                                                            W                  706                                +                                  W                  708                                                            W                706                                                    ,                            (        7        )            [1] Design Of Analog CMOS Integrated Circuits, McGraw-Hill 2001 [2] U.S. Pat. No. 6,445,244 [3] U.S. Pat. No. 6,559,684where W704 represents the channel width of switching device 704 and W710 represents the channel width of sensing device 710. When switching device 704 is not conducting and the drain voltage VD of switching device 704 goes high, then device 706 is turned off, thus shielding amplifier 714 from high input voltages. Therefore, the requirement for a high-speed, high-voltage amplifier is eliminated. However, the current-sense method shown in FIG. 7 could generally not be used for sensing a bi-directional power switch current Iswitch.
Many other problems and disadvantages of the prior art will become apparent to one skilled in the art after comparing such prior art with the present invention as described herein.